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Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
DESCRIPTION
The LF198/LF298/LF398 are monolithic sample-and-hold circuits which utilize high-voltage ion-implant JFET technology to obtain ultra-high DC accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, DC gain accuracy is 0.002% typical and acquisition time is as low as 6s to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin and does not degrade input offset drift. The wide bandwidth allows the LF198 to be included inside the feedback loop of 1MHz op amps without having stability problems. Input impedance of 1010 allows high source impedances to be used without degrading accuracy. P-channel junction FETs are combined with bipolar devices in the output amplifier to give droop rates as low as 5mV/min with a 1F hold capacitor. The JFETs have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design guarantees no feedthrough from input to output in the hold mode even for input signals equal to the supply voltages. Logic inputs are fully differential with low input current, allowing direct connection to TTL, PMOS, and CMOS; differential threshold is 1.4V. The LF198/LF298/LF398 will operate from 5V to 18V supplies. They are available in 8-pin plastic DIP, 8-pin Cerdip, and 14-pin plastic SO packages.
PIN CONFIGURATIONS
FE, N Packages
1 2 3 4 TOP VIEW 8 7 6 5
V+ OFFSET VOLTAGE INPUT V-
LOGIC LOGIC REFERENCE Ch OUTPUT
D1 Package
INPUT 1 NC 2 V- 3 NC 4 NC 5 NC 6 OUTPUT 7 TOP VIEW 14 V OS Adj 13 NC 12 V+ 11 LOGIC 10 LOGIC REF 9 8 NC Ch
FEATURES
* Operates from 5V to 18V supplies * Less than 10s acquisition time * TTL, PMOS, CMOS compatible logic input * 0.5mV typical hold step at CH=0.01F * Low input offset * 0.002% gain accuracy * Low output noise in hold mode * Input characteristics do not change during hold mode * High supply rejection ratio in sample or hold * Wide bandwidth
ORDERING INFORMATION
DESCRIPTION 8-Pin Ceramic Dual In-Line Package (CERDIP) 14-Pin Plastic Small Outline (SO) Package 8-Pin Ceramic Dual In-Line Package (CERDIP) 8-Pin Plastic Dual In-Line Package (DIP) 8-Pin Ceramic Dual In-Line Package (CERDIP) 8-Pin Plastic Dual In-Line Package (DIP)
NOTE: 1. SO and non-standard pinouts.
APPLICATION
* The LF198/LF298/LF398 are ideally suited for a wide variety of
sample-and-hold applications, including data acquisition, analog-to-digital conversion, synchronous demodulation, and automatic test setup
TEMPERATURE RANGE -55C to +125C 0 to +70C 0 to +70C 0 to +70C -25C to +85C -25C to +85C
ORDER CODE LF198FE LF398D LF398FE LF398N LF298FE LF298N
DWG # 0580A 0175D 0580A 0404B 0580A 0404B
August 31, 1994
879
853-0135 13721
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
FUNCTIONAL DIAGRAM
OFFSET
TYPICAL APPLICATIONS
V+ 30k - + 3 INPUT 8 LOGIC LOGIC 7 REFERENCE 6 HOLD CAPACITOR 300 SAMPLE 5V HOLD 0V LOGIC INPUT 8 7 ANALOG INPUT 3 S/H 5 OUTPUT 1 4 5 6 Ch OUTPUT V-
ABSOLUTE MAXIMUM RATINGS
SYMBOL VS Supply voltage Maximum power dissipation TA=25C (still-air)3 F package N package D package TA Operating ambient temperature range LF198 LF298 LF398 TSTG VIN Storage temperature range Input voltage Logic-to-logic reference differential voltage2 Output short-circuit duration Hold capacitor short-circuit duration TSOLD Lead soldering temperature (10sec max) -55 to +125 -25 to +85 0 to +70 -65 to +150 Equal to supply voltage +7, -30 Indefinite 10 300 sec C V C C C C 780 1160 1040 mW mW mW PARAMETER RATING 18 UNIT V
NOTES: 1. The maximum junction temperature of the LF398 is 150C. When operating at elevated ambient temperature, the packages must be derated based on the thermal resistance specified. 2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least 2V below the positive supply and 3V above the negative supply. 3. Derate above 25C, at the following rates: F package at 6.2mW/C N package at 9.3mW/C D package at 8.3mW/C
August 31, 1994
880
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following conditions apply: unit is in "sample" mode; VS = 15V; TJ = 25C; -11.5V3 VIN +11.5V; CH=0.01F; and RL = 10k. Logic reference voltage = 0V and logic voltage = 2.5V. SYMBOL VOS IBIAS PARAMETER Input offset voltage4 Input bias current4 Input impedance Gain error Feedthrough attenuation ratio at 1kHz Output impedance "HOLD" step2 ICC Supply current4 Logic and logic reference input current Leakage current into hold capacitor4 tAC Acquisition time to 0.1% Hold capacitor charging current Supply voltage rejection ratio Differential logic threshold TEST CONDITIONS TJ=25C Full temperature range TJ=25C Full temperature range TJ=25C TJ=25C, 1010 0.002 0.005 0.02 86 96 0.5 0.5 4.5 2 30 4 20 5 80 0.8 110 1.4 2.4 80 0.8 2 4 2.0 5.5 10 100 1.0 4.5 2 30 4 20 5 110 1.4 2.4 80 90 0.5 4 6 2.5 6.5 10 200 5 LF198/LF298 Min Typ 1 Max 3 5 25 75 1010 0.004 0.01 0.02 10 Min LF398 Typ 2 Max 7 10 50 100 UNIT mV nA % dB mV mA A pA s mA dB V
RL=10k
Full temperature range TJ=25C, Ch=0.01F TJ=25C, "HOLD" mode Full temperature range TJ=25C, Ch=0.01F, VOUT=0 TJ 25C TJ = 25C TJ=25C, "HOLD" mode VOUT=10V, Ch=1000pF Ch=0.01F VIN-VOUT=2V VOUT=0 TJ=25C
NOTES: 1. Unless otherwise specified, the following conditions apply. Unit is in "sample" mode, VS=15V, TJ=25C, -11.5V VIN +11.5V, Ch = 0.01F, and RL = 10k. Logic reference voltage = 0V and logic voltage = 2.5V. 2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an additional 0.5mV step with a 5V logic swing and a 0.01F hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. 3. Leakage current is measured at a junction temperature of 25C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25C value for each 11C increase in chip temperature. Leakage is guaranteed over full input signal range. 4. The parameters are guaranteed over a supply voltage of 5 to 18V.
August 31, 1994
881
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
TYPICAL DC PERFORMANCE CHARACTERISTICS
Input Bias Current
25 20 15 CURRENT (mA) 10 5 0 -5 -10 -15 -50 -25 0 25 50 75 100 125 150 CURRENT (mA) 20 18 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 SINKING SOURCING
Output Short Circuit Current
INPUT VOLTAGE -- OUTPUT VOLTAGE (mV) 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -15 -10
Gain Error
TJ = 25C RL = 10k SAMPLE MODE
-5
0
5
10
15
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
INPUT VOLTAGE (V)
Hold Step
100 V+ = V- = 15V TJ = 25C 10 HOLD STEP (mV) CURRENT (nA) 10 100
Leakage Current Into Hold Capacitor
2 VS = 15V VOUT = 0 HOLD MODE NORMALIZED HOLD STEP AMPLITUDE 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -25 0 25 50 75 100 125 150 -15
Hold Step Input Voltage
TJ = 100C
1
1
TJ = 25C
0.1
10-1
TJ = 55C
0.01 100pF
1000pF
0.01F
0.1F
1F
10-2 -50
-10
-5
0
5
10
15
HOLD CAPACITOR
JUNCTION TEMPERATURE (C)
INPUT VOLTAGE (V)
TYPICAL AC PERFORMANCE CHARACTERISTICS
Acquisition Time
1 VIN = 0 TO 10V 1% 10 TIME ( s) TJ = 25C 250 V+ = V- = 15V 225 200 TIME (ns) 0.1% 175 150 125 100 75 50 25 1000 0.001 0.01 HOLD CAPACITOR (F) 0.1 0 -50 -25 0 25 50 POSITIVE INPUT STEP 0.1 75 100 125 150 0.1 1 10 100 1 NEGATIVE INPUT STEP VOUT 1mV VIN = 10V
Aperture Time
100
Capacitor Hysteresis
10
0.01%
100
JUNCTION TEMPERATURE (C)
SAMPLE TIME (ms)
August 31, 1994
882
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
TYPICAL AC PERFORMANCE CHARACTERISTICS (Continued)
Dynamic Sampling Error
100 10 0
Output Droop Rate
2 1.8
`Hold' Sampling Time
330pF
V+ = V- = 15V SETTLING TIME
10 V/ T (V/SEC) ERROR (mV) 330pF 1
10-1 TIME ( s) TJ =85C 10-2 TJ =25C 10-3 1000pF 10-4 0.1 1 10 100 1000 100pF 1000pF 0.01F 0.1F 1F INPUT SLEW RATE (V/ms) HOLD CAPACITOR
1.6 1.4 1.2 1 0.8 0.6 0.4 0.2
-10
-100
0 -50 -25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (C)
Phase And Gain (Input to Output, Small-Signal)
5 Ch = 0 GAIN -- INPUT TO OUTPUT (dB) 0 -5 -10 Ch = 1000pF Ch 0.01F Ch = 1000pF Ch = 0.01F 80 70 60 50 40 30 20 10 Ch = 0 0 1k 10k 100k 1M 10M 160 140 REJECTION RATIO (dB) 120 100 80 60 40 20 INPUT TO OUTPUT PHASE DELAY ( o )
Power Supply Rejection
160 TJ =25C V+ = V- = 15V VOUT = 0C NOISE (nV/ Hz) 140 120 100
Output Noise
POSITIVE MODE NEGATIVE MODE
`HOLD' MODE 80 60 40 20 0 SAMPLE MODE
Ch 0.01F
0 100
1k
10k
100k
1M
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
Feedthrough Rejection Ratio (Hold Mode)
-130 V+ = V- = 15V -120 -110 RATIO (dB) Ch = 0.1F -100 -90 -80 Ch = 1000pF -70 -60 -50 10 100 100 1k 10k 100k 1M FREQUENCY (Hz) Ch = 0.01F TJ =25C VIN = 10Vp-p V7.8 = 0
August 31, 1994
883

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